The design of a sigma delta digital-to-analog (D/A) converter requires an interpolating filter that reduces the images of the signal at the input of the digital modulator. A cascaded integrator-comb (CIC) interpolating filter is a type of digital linear phase finite impulse response (FIR) filter which can be used in a sigma delta D/A converter to perform filtering and interpolating functions. In contrast to a CIC decimation filter of a sigma delta analog-to-digital (A/D) converter, the digital filtering requirements of the sigma delta D/A converter may be governed more by the system's power spectral density specification than by the need to filter quantization noise. Cascaded CIC interpolation filters are often used to perform this interpolating/filtering function because they are simple and economical (no multipliers are required). As the interpolating rate increases, however, the CIC filter digital word width grows rapidly.
FIG. 1 illustrates, in partial block diagram form and partial logic diagram form, a D/A converter 99 having a CIC interpolation filter in accordance with the prior art. D/A converter 99 includes a differentiator 100, an up-sampler 114, an integrator 116, a scalar 130, and a sigma delta D/A converter 132. The CIC interpolation filter portion of D/A converter 99 includes differentiator 100, up-sampler 114, and integrator 116. Differentiator 100 is a fourth order differentiator and includes stages 102, 108, 110, and 112. Stage 102 includes delay element 106 and adder 104. The other differentiator stages are substantially the same as stage 102. Differentiator stage 102 is a conventional differentiator which subtracts a delayed version of a digital word labeled "DIGITAL INPUT" from the DIGITAL INPUT and provides a difference output to the next stage of differentiator 100. The number of output bits between each of the stages increases because the digital word width is growing after each differentiation. The increased width of each subsequent differentiator stage is necessary to avoid overflow and retain accuracy during the differentiation. The output of differentiator 100 is provided to an input of up-sampler 114. Up-sampler 114 up-samples the sample frequency (f.sub.s) at a rate labeled "R" and provides an output to the input of integrator 116 having a frequency of R*f.sub.s.
The operation of D/A converter 99 can be better understood with reference to FIGS. 2-1 through 2-3. FIGS. 2-1 through 2-3 illustrate waveforms of various signals of prior art D/A converter 99 of FIG. 1. Note that f.sub.s is the sample frequency of differentiator 100. The variable R is the integer rate change factor and can be any number. Illustrated in FIG. 2-1 is the output of differentiator 100 labeled "A", and corresponds with the output of differentiator 100 illustrated in FIG. 1. The output of up-sampler 114 is labeled "B" and is illustrated in FIG. 2-2. The waveform B in FIG. 2--2 illustrates the frequency response of the output of up-sampler 114. The up-sampling operation causes the spectral energy from 0 to f.sub.s to replicate at intervals of f.sub.s to R times f.sub.s, where R is the up-sampling ratio. Because up-sampler 114 also includes a sample-and-hold circuit, the spectral images at intervals of f.sub.s are multiplied by a sin(x)/x function, where the zeros of the sin(x)/x function will occur at a multiple of the sample frequency f.sub.s. The number of bits entering up-sampler 114 is 20. FIG. 1 illustrates the case where R=200. If R equals 200, an 8 bit increase in the number of bits from the input of up sampler 114 to the input of integrator 116 is necessary.
Integrator 116 includes integrator stages 118, 124, 126, and 128. Stage 118 includes delay element 122 and adder 120. Each of the subsequent integrator stages are substantially the same as integrator state 118. As with differentiator 100, a number of bits need to be added from one stage to the next to avoid overflow and retain accuracy. By the time the output of integrator 116 is reached, a total of 47 bits are required, and are provided to an input of scalar 130. The 47 bit register and all of the registers from each of the previous stages are being clocked at a rate equal to R times frequency f.sub.s.
Scalar 130 is used to reduce the number of bits from integrator 116 to 16 bits. The output of scalar 130 is labeled "C" and is illustrated in FIG. 2-3. Scalar 130 is implemented as a 31 bit shift left in the illustrated embodiment. Sigma delta D/A converter 132 performs a conventional D/A conversion to provide an output labeled "ANALOG OUTPUT".
A problem with CIC interpolating filter 99 is that, by clocking the integrator 116 at a very high rate with a large number of bits, implementation problems occur because of the large number of bits required for each the adders for each integration stage. For example, for R=200, the adder of stage 128 must be 47 bits wide, the adder of stage 126 is 40 bits wide, the adder of stage 124 is 34 bits wide, and the adder of stage 118 is 28 bits wide. Also, operating these large adders at a high frequency consumes a large amount of power. In addition, implementing integrator 116 with large adders requires a relatively large surface area of an integrated circuit having CIC interpolating filter 99, which increases manufacturing costs and the size of the integrated circuit. In addition, when R=200, the frequency of the output of integrator 116 will be 200 times f.sub.s. Therefore, integrator 116 should be implemented in a very high speed process which can be very expensive to manufacture.